1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that is best suited in mounting a plurality of memory devices that require a refresh operation, for example Dynamic Random Access Memories (DRAMs) among memory devices in a System on Chip (SOC) of the semiconductor integrated circuit.
2. Description of the Related Art
FIG. 25 shows a conventional semiconductor integrated circuit. In FIG. 25, reference numerals 100 and 3001 represent a logic circuit and a DRAM, respectively. The logic circuit 100 controls a read/write operation and a refresh operation to the DRAM 3001. Symbol SLEEP represents a self-refresh control signal; NCEn, a read/write enable signal; CLK, a clock signal; and NREFn, a refresh enable signal.
The conventional semiconductor integrated circuit has a mode to perform the refresh operation even when the logic circuit 100 does not apply a cyclic signal to the clock signal CLK. In other words, the semiconductor integrated circuit includes a refresh timer within the DRAM 3001 which has the mode to perform the refresh operation by internally generating a clock signal corresponding to the clock signal CLK (for example, Patent Document 1).
FIG. 26 shows an internal circuit of the DRAM 3001 mounted on the conventional semiconductor integrated circuit. In FIG. 26, reference numeral 3101 represents a command decoder. Various control signals for the DRAM 3001 are inputted to the command decoder 3101, so that the command decoder 3101 recognizes an operation mode and outputs a predetermined signal.
FIG. 27 shows an example of the command decoder 3101. In FIG. 27, reference numerals 3201 and 3202 represent a refresh timer, and a selector, respectively and symbol iSCLK represents a self-refresh clock signal. The command decoder 3101 generates a cyclic clock as the self-refresh clock signal iSCLK when the self-refresh control signal SLEEP, which is connected to the refresh timer 3201, is at H level. The selector 3202 selects the self-refresh clock signal iSCLK instead of the clock signal CLK when the self-refresh control signal SLEEP is at H level. Thus, the DRAM 3001 performs the clock operation regardless of whether or not the clock signal CLK is provided.
Patent Document 1: Japanese Patent Application No. 2001-351826 (Japanese Unexamined Patent Publication (Kokai) No. 2003-157698)
Since a plurality of DRAMs are arranged in the conventional semiconductor integrated circuit, the circuit includes a plurality of refresh timers each mounted in the DRAM. Typically, the refresh timer is required to generate the refresh clock with a relatively long period for an operation clock to reduce power consumption. A RC delay circuit composed of a resistance and a capacitance is therefore used in many cases. In this case, an increase in circuit area will often cause a problem. Another problem is that, when the plurality of DRAMs perform the refresh operation at once, the plurality of DRAMs may simultaneously operate depending on the timing to increase a peak current, so that malfunction may occur due to a voltage drop.